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scripts/xx.json
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scripts/xx.json
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{
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"ROWS": [
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[
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"XC4VFX60",
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"Virtex IV FPGA 90<39>m CMOS",
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"Xilinx",
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"10/26/2006;IUCF07MAR;2007JUL",
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"M102606_XC4VFX60.pdf;T021607_XC4VFX60.pdf;nsrec07_W27_SEE.pdf;IU032707_XC4VFX60.pdf;nsrec08_W3_SEE.pdf;G07JUL_XC4VFX60_TID.pdf;nsrec08_W2_TID.pdf",
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"TID; SEE; SEFI",
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"90<39>m CMOS"
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],
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[
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"XC4VLX25",
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"Virtex IV FPGA",
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"Xilinx",
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"TAMU07AUG;IUCF07AUG;IUCF07OCT",
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"I032706_LX25_V2.pdf;nsrec08_W3_SEE.pdf",
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"SEE;SEL",
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"90nm CMOS"
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],
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[
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"XC5VLX30T-1FFG665GU",
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"Virtex V FPGA",
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"Xilinx",
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"TAMU09SEPT;UCD09JUN;IU09AUG",
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"D062209_XCVLX30T_na.pdf;nsrec2010_W8_SEE.pdf",
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"SEE;SEL;SEU",
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"65nm CMOS"
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],
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[
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"XC6SLX16",
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"FPGA",
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"Xilinx",
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"IU10MAR",
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"NEPP_DTRA_04062010_Berg.pdf;nsrec2011_W6_SEE.pdf",
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"SEE;SEL;SEU",
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"45nm CMOS"
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],
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[
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"XC7K325T Kintex7",
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"FPGA",
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"Xilinx",
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"4/5/2014;6/5/2014;12/16/2014;4/10/2015;8/12/2015;2016OctNRL",
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"https://nepp.nasa.gov/files/27025/2015-561-OBryan-Final-Paper-NEPPweb-NSREC2015DW-TN36350.pdf;https://nepp.nasa.gov/files/27964/NEPP-CP-2015-Berg-Presentation-SEE-MAPLD-TN23543.pdf;https://nepp.nasa.gov/files/28030/NEPP-CP-2015-Berg-Pres-NEPP-ETW-TN24313.pdf;https://nepp.nasa.gov/files/28239/NEPP-CP-2016-OBryan-Paper-NSREC-SEE-DW-TN35503.pdf;https://nepp.nasa.gov/workshops/etw2016/talks/14TUE/20160614-1330-FPGA-2016-561-Berg-Final-Pres-NEPP-ETW-FPGA_TN32953_v3.pdf;https://nepp.nasa.gov/files/28073/NEPP-CP-2016-Berg-Pres-MRQW-TN29375.pdf;https://nepp.nasa.gov/files/28290/NEPP-CP-2016-Berg-Pres-SEE-MAPLD-Mitigation-TN32695.pdf",
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"SEU",
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"CMOS"
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],
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[
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"XC7K325T-1FBG900 Kintex K7",
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"FPGA",
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"Xilinx",
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"2016Oct-Nov",
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"https://nepp.nasa.gov/files/29000/NEPP-CP-2017-OBryan-NSREC-SEE-DW-Paper-TN44942.pdf;https://nepp.nasa.gov/workshops/etw2017/talks/26-JUN-MON/1100%20-%20ETW_BERG_FPGA_SEU_TESTING_2017_EDAA.pdf;https://nepp.nasa.gov/files/28706/NEPP-CP-2017-Berg-SEE-MAPLD-FPGA-Presentation-TN42793.pdf;https://nepp.nasa.gov/files/28339/NEPP-CP-2016-Berg-Presentation-RADECS-TN35422.pdf;https://nepp.nasa.gov/files/28343/NEPP-CP-2016-Berg-Paper-RADECS-Proc-TN35827.pdf",
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"SEU;SEL",
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"28nm planar"
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],
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[
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"XCKU040-1LFFVA1156I Kintex-UltraScale",
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"FPGA",
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"Xilinx",
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"10/1/2016(TAMU); 3/1/2017(TAMU); 3/22/2017(TAMU); 12/6/2017(TAMU); 2017(Chicago); 4/29/2018(MGH); 5/1/2018(TAMU); 11/18/2019(LBNL)",
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"https://nepp.nasa.gov/docs/tasks/051-Compendium-SEE-TID-DD/NEPP-CP-2019-Topper-NSREC-Paper-TID-SEE-DD-Compendium-NSREC-TN70538.pdf;CP-2018-OBryan-NSREC-SEE-DW-Paper-20205001490.pdf;https://nepp.nasa.gov/files/29000/NEPP-CP-2017-OBryan-NSREC-SEE-DW-Paper-TN44942.pdf;https://nepp.nasa.gov/files/29516/NEPP-TR-2017-Berg-15-061-XCKU040-2FFVA1156-Kintex-UltraScale-TN45195.pdf",
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"SEE;SEU;SEFI;SEL",
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"20nm CMOS"
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],
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[
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"XCKU040-2FFVA1156E Kintex-UltraScale",
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"FPGA",
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"Xilinx",
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"11/18/2019",
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"2020-Topper-NSREC-TID-SEE-Compendium-DW-Paper-20205007136.pdf;https://nepp.nasa.gov/docs/tasks/041-FPGA/NEPP-TR-2019-Berg-TR-15-061-Xilinx-XCKU040-2FFVA1156E-KintexUltraScale-LBNL-2019Nov18-20205007765.pdf",
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"SEE",
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"FPGA"
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],
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[
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"XFM-5050-UV",
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"AlGaN 280 nm LED",
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"Luminus",
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"2023Aug(UDC)",
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"2024-OBryan-NSREC-DW-Compendium-Paper-20240008405.pdf",
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"DD",
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"Photonics"
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],
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[
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"XPA-II",
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"ASIC",
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"AMIS",
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"VdG2008AUG",
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"tid/VdG08AUG_XPAII.pdf;nsrec09_W13_TID.pdf",
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"TID",
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"0.18µm CMOS"
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],
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[
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"XQR4036XL",
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"FPGA",
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"Xilinx",
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"9/6/1998",
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"http://www.klabs.org/richcontent/fpga_content/Xilinx/SEE_Test_XR4036XL.pdf",
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"SEE",
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"FPGA"
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],
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[
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"XQV5FX70T",
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"FPGA",
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"Xilinx",
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"12/16/2014",
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"https://nepp.nasa.gov/files/27025/2015-561-OBryan-Final-Paper-NEPPweb-NSREC2015DW-TN36350.pdf;https://nepp.nasa.gov/files/27964/NEPP-CP-2015-Berg-Presentation-SEE-MAPLD-TN23543.pdf;https://nepp.nasa.gov/files/28030/NEPP-CP-2015-Berg-Pres-NEPP-ETW-TN24313.pdf",
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"SEE",
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"CMOS"
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],
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[
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"XQVR300",
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"FPGA",
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"Xilinx",
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"10/28/2000",
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"http://rk.gsfc.nasa.gov/richcontent/papers/Xilinx/Xilinx_NSREC2000.pdf",
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"TID;SEL;SEU",
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"FPGA"
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],
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[
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"Xilinx SIRF Test Transistors",
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"Test Transistors",
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"Xilinx",
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"VdG2008JUN",
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"tid/VdG08JUN_Xilinx_SIRF.pdf;nsrec09_W13_TID.pdf",
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"TID",
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"Transistor"
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],
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[
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"ZQ04031",
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"32kx8 SRAM",
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"Elmo/Hitachi",
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"11/7/1991",
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"tid/PPM-91-702.pdf",
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"TID",
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"Memory"
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],
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[
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"ZT-6500",
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"CPCI Pentium Processor",
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"Ziatech",
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"9/1/1997",
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"NSREC99.pdf",
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"SEE",
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"Board"
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],
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[
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"ZYNQ XC7Z020-1CLG400C",
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"FPGA and ARM Processor on TUL PYNQ-Z2 Board",
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"Xilinx",
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"8/19/2023(MGH)",
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"2024-OBryan-NSREC-DW-Compendium-Paper-20240008405.pdf;https://nepp.nasa.gov/docs/tasks/065-GPU-Devices/NEPP-NASA-TM-20-004-Xilinx-ZYNQ-XC7Z020-1CLG400C-SEE-Test-Report-MGH-2023Aug-20230013162.pdf",
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"SEE",
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"CMOS"
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],
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[
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"i3-5005U Broadwell 5th Gen Core™",
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"Processor",
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"Intel",
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"2015MGH;TRIUMF;HUPTI;Scripps;2015AugTAMU;2015DecTAMU;2016MayTAMU",
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"https://nepp.nasa.gov/files/28239/NEPP-CP-2016-OBryan-Paper-NSREC-SEE-DW-TN35503.pdf;https://nepp.nasa.gov/files/28007/NEPP-CP-2015-Szabo-Paper-DW-TN24989.pdf",
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"Proton Facility Evaluation",
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"14nm Gen 5 CMOS and FinFET"
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],
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[
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"i3-6100 Skylake 6th Gen Core™",
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"Processor",
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"Intel",
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"2015Dec",
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"https://nepp.nasa.gov/files/28239/NEPP-CP-2016-OBryan-Paper-NSREC-SEE-DW-TN35503.pdf",
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"Proton Facility Evaluation",
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"14nm Gen 6 CMOS and FinFET"
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],
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[
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"i3-6100T Skylake 6th Gen Core™",
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"Processor",
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"Intel",
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"2016MayTAMU;2016MayScripps",
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"https://nepp.nasa.gov/files/28239/NEPP-CP-2016-OBryan-Paper-NSREC-SEE-DW-TN35503.pdf",
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"Proton Facility Evaluation",
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"14nm Gen 6 CMOS and FinFET"
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],
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[
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"i5-6600K Skylake 6th Gen Core™",
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"Processor",
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"Intel",
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"2015NovTRIUMF",
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"https://nepp.nasa.gov/files/28239/NEPP-CP-2016-OBryan-Paper-NSREC-SEE-DW-TN35503.pdf",
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"Proton Facility Evaluation",
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"14nm Gen 6 CMOS and FinFET"
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],
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[
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"v1202b",
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"CPU",
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"AMD",
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"5/28/2022",
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"https://nepp.nasa.gov/docs/tasks/051-Compendium-SEE-TID-DD/NEPP-CP-2023-OBryan-Paper-NSREC-DW-Compendium-SEE-TID-20230009904.pdf;https://nepp.nasa.gov/docs/tasks/065-GPU-Devices/2022-Wyrwas-NASA-TM-20-005-AMD-v1202b-SoC-Proton-Test-Report-20230000488.pdf",
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"SEE",
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"CMOS"
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]
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],
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"PAGE": 1,
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"TOTAL": 1,
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"RECORDS": 1768
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}
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