{ "ROWS": [ [ "XC4VFX60", "Virtex IV FPGA 90�m CMOS", "Xilinx", "10/26/2006;IUCF07MAR;2007JUL", "M102606_XC4VFX60.pdf;T021607_XC4VFX60.pdf;nsrec07_W27_SEE.pdf;IU032707_XC4VFX60.pdf;nsrec08_W3_SEE.pdf;G07JUL_XC4VFX60_TID.pdf;nsrec08_W2_TID.pdf", "TID; SEE; SEFI", "90�m CMOS" ], [ "XC4VLX25", "Virtex IV FPGA", "Xilinx", "TAMU07AUG;IUCF07AUG;IUCF07OCT", "I032706_LX25_V2.pdf;nsrec08_W3_SEE.pdf", "SEE;SEL", "90nm CMOS" ], [ "XC5VLX30T-1FFG665GU", "Virtex V FPGA", "Xilinx", "TAMU09SEPT;UCD09JUN;IU09AUG", "D062209_XCVLX30T_na.pdf;nsrec2010_W8_SEE.pdf", "SEE;SEL;SEU", "65nm CMOS" ], [ "XC6SLX16", "FPGA", "Xilinx", "IU10MAR", "NEPP_DTRA_04062010_Berg.pdf;nsrec2011_W6_SEE.pdf", "SEE;SEL;SEU", "45nm CMOS" ], [ "XC7K325T Kintex7", "FPGA", "Xilinx", "4/5/2014;6/5/2014;12/16/2014;4/10/2015;8/12/2015;2016OctNRL", "https://nepp.nasa.gov/files/27025/2015-561-OBryan-Final-Paper-NEPPweb-NSREC2015DW-TN36350.pdf;https://nepp.nasa.gov/files/27964/NEPP-CP-2015-Berg-Presentation-SEE-MAPLD-TN23543.pdf;https://nepp.nasa.gov/files/28030/NEPP-CP-2015-Berg-Pres-NEPP-ETW-TN24313.pdf;https://nepp.nasa.gov/files/28239/NEPP-CP-2016-OBryan-Paper-NSREC-SEE-DW-TN35503.pdf;https://nepp.nasa.gov/workshops/etw2016/talks/14TUE/20160614-1330-FPGA-2016-561-Berg-Final-Pres-NEPP-ETW-FPGA_TN32953_v3.pdf;https://nepp.nasa.gov/files/28073/NEPP-CP-2016-Berg-Pres-MRQW-TN29375.pdf;https://nepp.nasa.gov/files/28290/NEPP-CP-2016-Berg-Pres-SEE-MAPLD-Mitigation-TN32695.pdf", "SEU", "CMOS" ], [ "XC7K325T-1FBG900 Kintex K7", "FPGA", "Xilinx", "2016Oct-Nov", "https://nepp.nasa.gov/files/29000/NEPP-CP-2017-OBryan-NSREC-SEE-DW-Paper-TN44942.pdf;https://nepp.nasa.gov/workshops/etw2017/talks/26-JUN-MON/1100%20-%20ETW_BERG_FPGA_SEU_TESTING_2017_EDAA.pdf;https://nepp.nasa.gov/files/28706/NEPP-CP-2017-Berg-SEE-MAPLD-FPGA-Presentation-TN42793.pdf;https://nepp.nasa.gov/files/28339/NEPP-CP-2016-Berg-Presentation-RADECS-TN35422.pdf;https://nepp.nasa.gov/files/28343/NEPP-CP-2016-Berg-Paper-RADECS-Proc-TN35827.pdf", "SEU;SEL", "28nm planar" ], [ "XCKU040-1LFFVA1156I Kintex-UltraScale", "FPGA", "Xilinx", "10/1/2016(TAMU); 3/1/2017(TAMU); 3/22/2017(TAMU); 12/6/2017(TAMU); 2017(Chicago); 4/29/2018(MGH); 5/1/2018(TAMU); 11/18/2019(LBNL)", "https://nepp.nasa.gov/docs/tasks/051-Compendium-SEE-TID-DD/NEPP-CP-2019-Topper-NSREC-Paper-TID-SEE-DD-Compendium-NSREC-TN70538.pdf;CP-2018-OBryan-NSREC-SEE-DW-Paper-20205001490.pdf;https://nepp.nasa.gov/files/29000/NEPP-CP-2017-OBryan-NSREC-SEE-DW-Paper-TN44942.pdf;https://nepp.nasa.gov/files/29516/NEPP-TR-2017-Berg-15-061-XCKU040-2FFVA1156-Kintex-UltraScale-TN45195.pdf", "SEE;SEU;SEFI;SEL", "20nm CMOS" ], [ "XCKU040-2FFVA1156E Kintex-UltraScale", "FPGA", "Xilinx", "11/18/2019", "2020-Topper-NSREC-TID-SEE-Compendium-DW-Paper-20205007136.pdf;https://nepp.nasa.gov/docs/tasks/041-FPGA/NEPP-TR-2019-Berg-TR-15-061-Xilinx-XCKU040-2FFVA1156E-KintexUltraScale-LBNL-2019Nov18-20205007765.pdf", "SEE", "FPGA" ], [ "XFM-5050-UV", "AlGaN 280 nm LED", "Luminus", "2023Aug(UDC)", "2024-OBryan-NSREC-DW-Compendium-Paper-20240008405.pdf", "DD", "Photonics" ], [ "XPA-II", "ASIC", "AMIS", "VdG2008AUG", "tid/VdG08AUG_XPAII.pdf;nsrec09_W13_TID.pdf", "TID", "0.18µm CMOS" ], [ "XQR4036XL", "FPGA", "Xilinx", "9/6/1998", "http://www.klabs.org/richcontent/fpga_content/Xilinx/SEE_Test_XR4036XL.pdf", "SEE", "FPGA" ], [ "XQV5FX70T", "FPGA", "Xilinx", "12/16/2014", "https://nepp.nasa.gov/files/27025/2015-561-OBryan-Final-Paper-NEPPweb-NSREC2015DW-TN36350.pdf;https://nepp.nasa.gov/files/27964/NEPP-CP-2015-Berg-Presentation-SEE-MAPLD-TN23543.pdf;https://nepp.nasa.gov/files/28030/NEPP-CP-2015-Berg-Pres-NEPP-ETW-TN24313.pdf", "SEE", "CMOS" ], [ "XQVR300", "FPGA", "Xilinx", "10/28/2000", "http://rk.gsfc.nasa.gov/richcontent/papers/Xilinx/Xilinx_NSREC2000.pdf", "TID;SEL;SEU", "FPGA" ], [ "Xilinx SIRF Test Transistors", "Test Transistors", "Xilinx", "VdG2008JUN", "tid/VdG08JUN_Xilinx_SIRF.pdf;nsrec09_W13_TID.pdf", "TID", "Transistor" ], [ "ZQ04031", "32kx8 SRAM", "Elmo/Hitachi", "11/7/1991", "tid/PPM-91-702.pdf", "TID", "Memory" ], [ "ZT-6500", "CPCI Pentium Processor", "Ziatech", "9/1/1997", "NSREC99.pdf", "SEE", "Board" ], [ "ZYNQ XC7Z020-1CLG400C", "FPGA and ARM Processor on TUL PYNQ-Z2 Board", "Xilinx", "8/19/2023(MGH)", "2024-OBryan-NSREC-DW-Compendium-Paper-20240008405.pdf;https://nepp.nasa.gov/docs/tasks/065-GPU-Devices/NEPP-NASA-TM-20-004-Xilinx-ZYNQ-XC7Z020-1CLG400C-SEE-Test-Report-MGH-2023Aug-20230013162.pdf", "SEE", "CMOS" ], [ "i3-5005U Broadwell 5th Gen Core™", "Processor", "Intel", "2015MGH;TRIUMF;HUPTI;Scripps;2015AugTAMU;2015DecTAMU;2016MayTAMU", "https://nepp.nasa.gov/files/28239/NEPP-CP-2016-OBryan-Paper-NSREC-SEE-DW-TN35503.pdf;https://nepp.nasa.gov/files/28007/NEPP-CP-2015-Szabo-Paper-DW-TN24989.pdf", "Proton Facility Evaluation", "14nm Gen 5 CMOS and FinFET" ], [ "i3-6100 Skylake 6th Gen Core™", "Processor", "Intel", "2015Dec", "https://nepp.nasa.gov/files/28239/NEPP-CP-2016-OBryan-Paper-NSREC-SEE-DW-TN35503.pdf", "Proton Facility Evaluation", "14nm Gen 6 CMOS and FinFET" ], [ "i3-6100T Skylake 6th Gen Core™", "Processor", "Intel", "2016MayTAMU;2016MayScripps", "https://nepp.nasa.gov/files/28239/NEPP-CP-2016-OBryan-Paper-NSREC-SEE-DW-TN35503.pdf", "Proton Facility Evaluation", "14nm Gen 6 CMOS and FinFET" ], [ "i5-6600K Skylake 6th Gen Core™", "Processor", "Intel", "2015NovTRIUMF", "https://nepp.nasa.gov/files/28239/NEPP-CP-2016-OBryan-Paper-NSREC-SEE-DW-TN35503.pdf", "Proton Facility Evaluation", "14nm Gen 6 CMOS and FinFET" ], [ "v1202b", "CPU", "AMD", "5/28/2022", "https://nepp.nasa.gov/docs/tasks/051-Compendium-SEE-TID-DD/NEPP-CP-2023-OBryan-Paper-NSREC-DW-Compendium-SEE-TID-20230009904.pdf;https://nepp.nasa.gov/docs/tasks/065-GPU-Devices/2022-Wyrwas-NASA-TM-20-005-AMD-v1202b-SoC-Proton-Test-Report-20230000488.pdf", "SEE", "CMOS" ] ], "PAGE": 1, "TOTAL": 1, "RECORDS": 1768 }